1. Field of Invention
The present invention relates to a method for forming integrated circuit device. More particularly, the present invention relates to a method for forming a shallow trench isolation (STI) structure in a semiconductor substrate.
2. Description of Related Art
Device isolation regions are specially formed structures in a substrate for preventing carriers from moving between neighboring semiconductor devices. Normally, device isolation regions are formed within a dense semiconductor circuit region between neighboring field effect transistors (FETs) for reducing leakage current between them. Conventional isolation structure is a field oxide layer formed using a local oxidation of silicon (LOCOS) method. However, the field oxide layer produced by the LOCOS method often tends to accumulate internal stresses. Moreover, a bird's beak profile is formed close to the edge of the field oxide layer. The presence of a bird's beak near the edge of the field oxide layer makes device isolation almost impossible, especially when the device dimensions are small. Hence, in the fabrication of high-density circuits, field oxide structure is mostly replaced by a shallow trench isolation (STI) type of isolation structure.
Shallow trench isolation (STI) is one of the methods for forming device isolation structure in a semiconductor device. The method includes the steps of anisotropically etching a semiconductor substrate to form a trench, and then depositing insulating material to fill the trench. The STI structure has the advantage of being scaleable in addition to the capacity to avoid the bird's beak encroachment problem seen in conventional field oxide isolation. Therefore, STI is an ideal method for isolating sub-micron complementary MOS (CMOS) devices.
FIGS. 1A through 1D are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a shallow trench isolation region in a substrate. First, as shown in FIG. 1A, a pad oxide layer 102 is formed over a silicon substrate 100 using a thermal oxidation method. Thereafter, a silicon nitride mask layer 104 is formed over the pad oxide layer 102.
Next, as illustrated in FIG. 1B, a photoresist layer (not shown) is deposited over the mask layer 104. Then, the mask layer 104, the pad oxide layer 102 and the silicon substrate 100 are etched in sequence to form a patterned mask layer 104a, a patterned pad oxide layer 102a and a trench 108 in the substrate 100. Subsequently, the photoresist layer is removed.
Next, as shown in FIG. 1C, high-temperature oxidation is conducted to form a liner oxide layer 110 on the exposed substrate surface of the trench 108. Thereafter, silicon oxide material is deposited into the trench 108, and then a chemical-mechanical polishing operation is carried out to remove the excess oxide material. Subsequently, the silicon nitride mask 104a is removed using hot phosphoric acid solution, and then the pad oxide layer 102a is removed using hydrofluoric (HF) acid solution. Finally, an isolation region 112 is formed in the substrate 100.
In the aforementioned method of fabricating a device isolation region, hydrofluoric acid solution is used to remove the pad oxide layer 102a in a wet etching operation. Since oxide material inside the trench 108 is more loosely deposited than the pad oxide layer 102a, the etching rate of oxide inside the trench 108 may be higher than that of the pad oxide layer 102a. Moreover, hydrofluoric acid solution is an isotropic etchant. Therefore, recess cavities 115 are easily formed at the top corner regions 114 of the trench 108, and hence the top corner regions 114 of the trench 108 are exposed.
The top corner region 114 of the trench 108 has rather sharp cross-sectional profile, as shown in FIG. 1D. Since a region with a sharp corner tends to slow the oxidation rate in a thermal oxidation operation, the corner regions 114 are covered with a thinner oxide layer when a gate oxide layer 116 is formed over the substrate 100. Uneven thickness in the gate oxide layer 116 later produces abnormal subthreshold voltage leading to the intensification of what is known as the kink effect.
In light of the foregoing, there is a need to improve the method of forming shallow trench isolation structure.